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Mr. Sourabh Panwar | Chip Design Award | Best Researcher Award

Mr. Sourabh Panwar, Sardar Vallabhbhai National Institute of Technology, SVNIT, India

Sourabh Panwar is a skilled Teaching Assistant with diverse administrative experience, including roles such as Chief Proctor, Financial Committee member, and University Liaison at SVNIT Surat. He holds a Bachelor’s degree in Electronics Engineering from Government Engineering College, Bikaner, and a Master’s in Digital Communication from MBM Engineering College, Jodhpur. Currently pursuing a Ph.D. in VLSI at SVNIT Surat, his research focuses on device design and modeling of ferroelectric-based devices and Tunnel FETs. Sourabh has a strong publication record in prestigious journals and has presented his work at international workshops. He has also actively participated in workshops and training sessions related to his field, showcasing his expertise in TCAD simulation and academic collaboration. Sourabh’s accolades include receiving the GATE stipend for his research and winning prizes in tech fests and hackathons, highlighting his dedication and proficiency in academia and research.

Professional Profile:

Scopus

Google Scholar

šŸŽ“ Education:

Sourabh Panwar completed his Bachelor of Technology in Electronics Engineering from Government Engineering College, Bikaner, in 2013. He furthered his education by obtaining a Master of Engineering in Digital Communication from MBM Engineering College, Jodhpur, in 2017. Currently, Sourabh is pursuing a Doctor of Philosophy in VLSI at SVNIT Surat, showcasing a commitment to advancing his expertise in the field of electronics engineering.

šŸ‘Øā€šŸ« Previous Experience:

As an Assistant Professor at Government Engineering College, Barmer from 2018 to 2020, I focused on fostering academic and community collaborations with industries. My role involved mentoring students and facilitating industry partnerships to enhance practical learning experiences. Through these collaborations, students gained valuable insights into industry practices, which complemented their academic curriculum. By bridging the gap between academia and industry, I aimed to equip students with the skills and knowledge necessary to excel in their careers.

šŸ† Achievements:

As an Assistant Professor at Government Engineering College, Barmer from 2018 to 2020, I played a pivotal role in fostering academic and community collaborations with various industries. My focus was on creating synergies between academia and industry, ensuring students were exposed to real-world applications of their coursework. I actively mentored students, guiding them towards industry-relevant projects and internships, thereby facilitating valuable industry collaborations. This hands-on approach aimed to bridge the gap between theoretical knowledge and practical implementation, preparing students for the demands of the professional world.

Publication Top Notes:

  1. Proposal and investigation of area scaled nanosheet tunnel FET: A physical insight – 2022
    • Published in: IEEE Transactions on Electron Devices
    • Cited by: 16
  2. Investigation of field-free switching of 2-D material-based spinā€“orbit torque magnetic tunnel junction – 2023
    • Published in: IEEE Transactions on Electron Devices
    • Cited by: 5
  3. Performance evaluation of high-Īŗ dielectric ferro-spacer engineered Si/SiGe hetero-junction line TFETs: a TCAD approach – 2023
    • Published in: IEEE Transactions on Dielectrics and Electrical Insulation
    • Cited by: 4
  4. Influences of Source/Drain Extension Region on Thermal Behavior of Stacked Nanosheet FET – 2024
    • Published in: IEEE Transactions on Electron Devices
    • Cited by: 1
  5. Understanding the Impact of Extension Region on Stacked Nanosheet FET: Analog Design Perspective – 2023
    • Published in: Solid-State Electronics
    • Cited by: 1

 

 

 

 

Mr. Sourabh Panwar | Chip Design Award | Best Researcher Award

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