Mr. Narsimhulu Thoti | Nanoelectronics | Member
Mr. Narsimhulu Thoti, National Yang Ming Chiao Tung University, Taiwan
π§ Skill Set:
VLSI Laboratory & Advanced Processing Equipments. DC characterization of semiconductor devices. Device and process level modeling (Synopsys and Silvaco TCAD). Circuit simulation (Matlab) and numerical modeling (Matlab & C++). Circuit and layout level (digital) design and analysis (Cadence and Mentor Graphics). Circuit level verification (VHDL & Verilog).
π Research Area:
Device Physics and modeling of Tunneling FETs (TFETs), Negative Capacitance (NC)-FETs, CFET, and HEMTs. Circuit & Memory designs (CFET-inverter, SRAM, DRAM). Device fabrication and measurement (FETs, HEMTs). Machine learning for device modeling; Materials science for semiconductors (IV, III-V, 2D) and insulators (high-π , ferroelectric).
π¨βπ« Experience:
Assistant Professor at Siddharth Group of Institutions, India (2014-2016). Faculty at Kuppam Engineering College, India (2013-2014, 2011-2012).
π Achievements:
Certification in VLSI Laboratory Course-Advance Processing Equipments (Taiwan Semiconductor Research Institute, Taiwan, 2022). Excellent research student award (National Yang Ming Chiao Tung University, Taiwan, 2022 & 2021). Excellent poster paper award (IEDMS, NCKU, Taiwan, 2021). Best poster paper award (IWPSD, IIT Kharagpur, India, 2019). Outstanding foreign student scholarship award (National Yang Ming Chiao Tung University, Taiwan, 2019). Best paper award (National Conf., University of Delhi, India, 2017). GATE qualified with Institute Rank-1 (Indian Institute of Technology, 2014).
π Education:
Ph.D. in Semiconductor Devices, National Yang Ming Chiao Tung University (Expected 2023). M.Tech. in VLSI System Design, Jawaharlal Nehru Technological University (2011). B.Tech. in Electronics and Communication Engineering, Jawaharlal Nehru Technological University (2009).
π¬ Key Projects:
Design and modeling of Complementary TFETs. Modeling of vertical TFETs through machine learning. Breakdown analysis and buffer leakage in GaN HEMT structures. Design of energy-efficient area tunneling and ferroelectric TFETs. Device process variability analyses of GAAFETs. Implementation of compression algorithms for reduction of microprocessor latency. Embedded design for monitoring and controlling of home appliances through GSM.
The impact of her research is evident in citation metrics and indices from Google Scholar:
- Cited by: All β 181.
- Citations β 181.
- h-index β 9.
- Documents β 29.
A prolific researcher making meaningful contributions to the academic world!